Rainbow Electronics ATmega128RFA1 - Manual (Page 369)

369
8266A-MCU Wireless-12/09
ATmega128RFA1
24.2.1 Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver.
For USART MSPIM mode of operation only internal clock generation (i.e. master
operation) is supported. The Data Direction Register for the XCKn pin (DDR_XCKn)
must therefore be set to one (i.e. as output) for the USART in MSPIM to operate
correctly. Preferably the DDR_XCKn should be set up before the USART in MSPIM is
enabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART
synchronous master mode. The baud rate or UBRRn setting can therefore be
calculated using the same equations, see
Table 24-1 below :
Table 24-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Equation for Calculating
Baud Rate
(1)
Equation for Calculating
UBRR Value
Synchronous Master mode
) 1 ( 2 +
=
UBRRn
f
BAUD OSC 1
2
− =
BAUD
f
UBRRn OSC
Note: The Baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRRn Contents of the UBRRHn and UBRRLn Registers, (0-4095)
24.3 SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial
data, which are determined by control bits UCPHAn and UCPOLn. The data transfer
timing diagrams are shown in
Figure 24-1 below . Data bits are shifted out and latched
in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to
stabilize. The UCPOLn and UCPHAn functionality is summarized in
Table 24-2 below .
Note that changing the setting of any of these bits will corrupt all ongoing
communication for both the receiver and transmitter.
Figure 24-1. UCPHAn and UCPOLn data transfer timing diagrams
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
UCPOL=0 UCPOL=1
UCPHA=0
UCPHA=1
Table 24-2. UCPOLn and UCPHAn Functionality
UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge
0 0 0 Sample (Rising) Setup (Falling)
0 1 1 Setup (Rising) Sample (Falling)
1 0 2 Sample (Falling) Setup (Rising)