Rainbow Electronics ATmega128RFA1 - Manual (Page 154)

154
8266A-MCU Wireless-12/09
ATmega128RFA1
Register Bits Value Description
0xff Calibration value for highest oscillator
frequency
11.11.2 CLKPR – Clock Prescale Register
Bit 7 6 5 4 3 2 1 0
NA ($61) CLKPCE Res2 Res1 Res0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write RW R R R RW RW RW RW
Initial Value 0 0 0 0 0 0 0 0
• Bit 7 – CLKPCE - Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend
the time-out period, nor clear the CLKPCE bit.
• Bit 6:4 – Res2:0 - Reserved
• Bit 3:0 – CLKPS3:0 - Clock Prescaler Select Bits
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The
division factors are given in the following table. Note that the factor is different when
using the internal 16MHz RC oscillator as the clock source. The CKDIV8 Fuse
determines the initial value of the CLKPS bits. If CKDIV8 is not programmed, the
CLKPS bits will be reset to 0000. If CKDIV8 is programmed, CLKPS bits are reset to
0011 giving a division factor of 8 at start up. This feature should be used if the selected
clock source has a higher frequency than the maximum frequency of the device at the
present operating conditions. Note that any value can be written to the CLKPS bits
regardless of the CKDIV8 Fuse setting. The Application software must ensure that a
sufficient division factor is chosen if the selected clock source has a higher frequency
than the maximum frequency of the device at the present operating conditions. The
device is shipped with the CKDIV8 Fuse programmed.
Table 11-12 CLKPS Register Bits
Register Bits Value Description
0x0 Division factor 1 / RC-Oscillator 2
0x1 Division factor 2 / RC-Oscillator 4
0x2 Division factor 4 / RC-Oscillator 8
0x3 Division factor 8 / RC-Oscillator 16
0x4 Division factor 16 / RC-Oscillator 32
0x5 Division factor 32 / RC-Oscillator 64
0x6 Division factor 64 / RC-Oscillator 128
0x7 Division factor 128 / RC-Oscillator 256
0x8 Division factor 256 / RC-Oscillator 512
0x9 Reserved
CLKPS3:0
0xA Reserved