Renesas SH7641 - Manual (Page 913)

Section 23 I/O Ports
Rev. 4.00 Sep. 14, 2005 Page 863 of 982
REJ09B0023-0400
23.9.2 Port J Data Register (PJDR)
PJDR is a 13-bit readable/writable register with three reserved bits that stores data for pins PTJ12
to PTJ0. The PJDR is initialized to H'0000 by a power-on reset, but it retains its previous value by
a manual reset, in standby mode, or in sleep mode.
Bit Bit Name
Initial
Value R/W
Description
15 to 13  All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
12 PJ12DT 0 R/W
11 PJ11DT 0 R/W
10 PJ10DT 0 R/W
9 PJ9DT 0 R/W
8 PJ8DT 0 R/W
7 PJ7DT 0 R/W
6 PJ6DT 0 R/W
5 PJ5DT 0 R/W
4 PJ4DT 0 R/W
3 PJ3DT 0 R/W
2 PJ2DT 0 R/W
1 PJ1DT 0 R/W
0 PJ0DT 0 R/W
Bits PJ12DT to PJ0DT correspond to pins PTJ12 to
PTJ0. When the pin function is general output port, the
value of the corresponding bit in PJDR is returned
directly by reading the port. When the function is
general input port, the corresponding pin level is read
by reading the port. Table 23.12 shows the function of
PJDR.
Table 23.12 Port J Data Register (PJDR) Read/Write Operations
PJnMD2 PJnMD1 Pin State Read Write
0 0 Input Pin state Data is written to PJDR, but does not affect
pin state.
1 Output PJDR value Data is written to PJDR and the value is
output from the pin.
1 0 Reserved  
1 Other functions Pin state Data is written to PJDR, but does not affect
pin state.
(n = 0 to 12)