Renesas SH7641 User Manual
Page 109
Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 59 of 982
REJ09B0023-0400
Instruction Format
Source
Operand
Destination
Operand Sample
Instruction
mmmm
: register
direct
nnnn
: register
direct
ADD Rm,Rn
nm type
nnnn
xxxx
xxxx
15
0
mmmm
mmmm
: register
direct
nnnn
: register
indirect
MOV.L Rm,@Rn
mmmm
: post-
increment register
indirect (multiply-
and-accumulate
operation)
nnnn
: * post-
increment register
indirect (multiply-
and-accumulate
operation)
MACH, MACL
MAC.W @Rm+,@Rn+
mmmm
: post-
increment register
indirect
nnnn
: register
direct
MOV.L @Rm+,Rn
mmmm
: register
direct
nnnn
: pre-
decrement register
indirect
MOV.L Rm,@-Rn
mmmm
: register
direct
nnnn
: indexed
register indirect
MOV.L Rm,@(R0,Rn)
md type
xxxx
dddd
15
0
mmmm
xxxx
mmmmdddd
:
register indirect
with displacement
R0 (register direct) MOV.B @(disp,Rm),R0
nd4 type
dddd
nnnn
xxxx
15
0
xxxx
R0 (register direct) nnnndddd:
register indirect
with displacement
MOV.B R0,@(disp,Rn)
nmd type
nnnn
xxxx
dddd
15
0
mmmm
mmmm
: register
direct
nnnndddd
:
register indirect
with displacement
MOV.L Rm,@(disp,Rn)
mmmmdddd
:
register indirect
with displacement
nnnn
: register
direct
MOV.L @(disp,Rm),Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.