Renesas SH7641 - Manual (Page 144)

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 94 of 982
REJ09B0023-0400
Instruction
Instruction Code
Operation Execution
States
DC
PDEC Sy,Dz 111110 **********
1010100100yyzzzz
Sy [31:16] – 1 → Dz 1
*
DCT PDEC Sx,Dz 111110 **********
10001010xx00zzzz
If DC = 1, Sx [39:16] – 1
→ Dz
If DC = 0, nop 1 
DCT PDEC Sy,Dz 111110 **********
1010101000yyzzzz
If DC = 1, Sy [31:16] – 1
→ Dz
If DC = 0, nop 1 
DCF PDEC Sx,Dz 111110 **********
10001011xx00zzzz
If DC = 0, Sx [39:16] – 1
→ Dz
If DC = 1, nop 1 
DCF PDEC Sy,Dz 111110 **********
1010101100yyzzzz
If DC = 0, Sy [31:16] – 1
→ Dz
If DC = 1, nop 1 
PCLR Dz 111110 **********
100011010000zzzz
h'00000000 → Dz 1
*
DCT PCLR Dz 111110 **********
100011100000zzzz
If DC = 1, h'00000000 → Dz
If DC = 0, nop
1 
DCF PCLR Dz 111110 **********
100011110000zzzz
If DC = 0, h'00000000 → Dz
If DC = 1, nop
1 
PSHA #imm,Dz 111110 **********
00010iiiiiiizzzz
If imm > = 0, Dz << imm
→ Dz (arithmetic shift)
If imm<0, Dz>>imm
→ Dz
1 *
PSHL #imm,Dz 111110 **********
00000iiiiiiizzzz
If imm > = 0, Dz << imm
→ Dz (logical shift)
If imm < 0, Dz >> imm
→ Dz
1 *
PSTS MACH,Dz 111110 **********
110011010000zzzz
MACH → Dz 1 
DCT PSTS MACH,Dz 111110 **********
110011100000zzzz
If DC = 1, MACH
→ Dz 1 
DCF PSTS MACH,Dz 111110 **********
110011110000zzzz
If DC = 0, MACH
→ Dz 1 
PSTS MACL,Dz 111110 **********
110111010000zzzz
MACL
→ Dz 1 