Renesas SH7641 - Manual (Page 506)

Section 15 User Debugging Interface (H-UDI)
Rev. 4.00 Sep. 14, 2005 Page 456 of 982
REJ09B0023-0400
15.2 Input/Output Pins
Table 15.1 shows the pin configuration of the H-UDI.
Table 15.1 Pin Configuration
Pin Name Input/Output Description
TCK Input Serial data input/output clock pin
Data is serially supplied to the H-UDI from the data input pin
(TDI), and output from the data output pin (TDO), in
synchronization with this clock.
TMS Input Mode select input pin
The state of the TAP control circuit is determined by changing
this signal in synchronization with TCK. The protocol conforms
to the JTAG standard (IEEE Std.1149.1).
TRST
Input Reset input pin
Input is accepted asynchronously with respect to TCK, and
when low, the H-UDI is reset.
TRST must be low for a
constant period when power is turned on regardless of using
the H-UDI function. This is different from the JTAG standard.
See section 15.4.2, Reset Configuration, for more information.
TDI Input Serial data input pin
Data transfer to the H-UDI is executed by changing this signal
in synchronization with TCK.
TDO Output Serial data output pin
Data read from the H-UDI is executed by reading this pin in
synchronization with TCK. The data output timing depends on
the command type set in the SDIR. See section 15.3.2
Instruction Register (SDIR), for more information.
ASEMD0*
Input ASE mode select pin
If a low level is input at the
ASEMD0 pin while the RESETP
pin is asserted, ASE mode is entered; if a high level is input,
normal mode is entered. In ASE mode, dedicated emulator
function can be used. The input level at the
ASEMD0 pin
should be held for at least one cycle after
RESETP negation.
ASEBRKAK,
AUDSYNC,
AUDATA3 to
AUDATA 0,
AUDCK
Output Dedicated emulator pin
Note: * When the emulator is not in use, fix this pin to the high level.