Renesas SH7641 User Manual
Page 540
Section 16 I
2
C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 490 of 982
REJ09B0023-0400
TDRE
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
TEND
[5] Write data to ICDRT (third byte)
ICDRT
ICDRS
[2] Instruction of start
condition issuance
[3] Write data to ICDRT (first byte)
[4] Write data to ICDRT (second byte)
User
processing
1
Bit 7
Slave address
Address + R/
W
Data 1
Data 1
Data 2
Address + R/
W
Bit 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2
1
2
3
4
5
6
7
8
9
A
R/
W
Figure 16.5 Master Transmit Mode Operation Timing (1)
TDRE
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
TEND
ICDRT
ICDRS
1
9
2
3
4
5
6
7
8
9
A
A/
A
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7
Bit 6
Data n
Data n
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
[5] Write data to ICDRT
User
processing
Figure 16.6 Master Transmit Mode Operation Timing (2)