Renesas SH7641 - Manual (Page 309)

Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 259 of 982
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word data in bits 31 to 16 in BDRB and BDMRB when including the value of the data bus as a
break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or
MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored).
4. Access by a PREF instruction is handled as read access in longword units without access data.
Therefore, if including the value of the data bus when a PREF instruction is specified as a
break condition, a break will not occur.
5. If the L bus is selected, a break occurs on ending execution of the instruction that matches the
break condition, and immediately before the next instruction is executed. However, when data
is also specified as the break condition, the break may occur on ending execution of the
instruction following the instruction that matches the break condition. If the I bus is selected,
the instruction at which the break will occur cannot be determined. When this kind of break
occurs at a delayed branch instruction or its delay slot, the break may not actually take place
until the first instruction at the branch destination.
11.3.4 Break on X/Y-Memory Bus Cycle
1. The break condition on an X/Y-memory bus cycle is specified only in channel B. If the XYE
bit in BBRB is set to 1, the break address and break data on X/Y-memory bus are selected. At
this time, select the X-memory bus or Y-memory bus by specifying the XYS bit in BBRB. The
break condition cannot include both X-memory and Y-memory at the same time. The break
condition is applied to an X/Y-memory bus cycle by specifying L bus/data access/read or
write/word or no specified operand size in bits 7 to 0 in the break bus cycle register B (BBRB).
2. When an X-memory address is selected as the break condition, specify an X-memory address
in the upper 16 bits in BARB and BAMRB. When a Y-memory address is selected, specify a
Y-memory address in the lower 16 bits. Specification of X/Y-memory data is the same for
BDRB and BDMRB.
3. The timing of a data access break for the X memory or Y memory bus to occur is the same as a
data access break of the L bus. For details, see 5 in section 11.3.3, Break on Data Access
Cycle.