Renesas SH7641 - Manual (Page 751)

Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 701 of 982
REJ09B0023-0400
Bit Bit Name
Initial
value R/W Description
6 TEND 0 R/(W)* Transmit End
Indicates that when the last bit of a serial character
was transmitted, SCFTDR did not contain valid data,
so transmission has ended.
0: Transmission is in progress
[Clearing condition]
• TEND is cleared to 0 when 0 is written after 1 is
read from TEND after transmit data is written in
SCFTDR
1: End of transmission
[Setting conditions]
• TEND is set to 1 when the chip is a power-on
reset
• TEND is set to 1 when TE is cleared to 0 in the
serial control register (SCSCR)
• TEND is set to 1 when SCFTDR does not contain
receive data when the last bit of a one-byte serial
character is transmitted
Note: When the transmit FIFO data empty DMA
transfer request is generated and transmit
data is written to SCFTDR by the DMAC, do
not use this flag as a transmit end flag.