Renesas SH7641 - Manual (Page 372)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 322 of 982
REJ09B0023-0400
Table 12.6 16-Bit External Device Access and Data Alignment
Data Bus Strobe Signals
Operation
D31 to
D24 D23 to
D16 D15 to
D8 D7
to D0
WE3
,
DQMUU
WE2
,
DQMUL
WE1
,
DQMLU
WE0
,
DQMLL
Byte access at 0   Data
7 to 0
   Assert 
Byte access at 1    Data
7 to 0
   Assert
Byte access at 2   Data
7 to 0
   Assert 
Byte access at 3    Data
7 to 0
   Assert
Word access at 0   Data
15 to 8
Data
7 to 0
  Assert Assert
Word access at 2   Data
15 to 8
Data
7 to 0
  Assert Assert
1st
time at 0   Data
31 to 24
Data
23 to 16
  Assert Assert Longword
access at 0
2nd
time at 2   Data
15 to 8
Data
7 to 0
  Assert Assert