Renesas SH7641 - Manual (Page 314)

Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 264 of 982
REJ09B0023-0400
(Example 1-5)
• Register specifications
BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000,
BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000001, BETR = H'0005
Specified conditions: Channel A/channel B independent mode
Address: H'00000500, Address mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
Address: H'00001000, Address mask: H'00000000
Data: H'00000000, Data mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword
The number of execution-times break enable (5 times)
On channel A, a user break occurs before an instruction of address H'00000500 is executed.
On channel B, a user break occurs after the instruction of address H'00001000 are executed
four times and before the fifth time.
(Example 1-6)
• Register specifications
BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010,
BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,
BRCR = H'00000400
Specified conditions: Channel A/channel B independent mode
Address: H'00008404, Address mask: H'00000FFF
Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
Address: H'00008010, Address mask: H'00000006
Data: H'00000000, Data mask: H'00000000
Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed
or before an instruction with addresses H'00008010 to H'00008016 are executed.