Renesas SH7641 - Manual (Page 254)

Section 9 Exception Handling
Rev. 4.00 Sep. 14, 2005 Page 204 of 982
REJ09B0023-0400
Table 9.1 Exception Event Vectors
Exception
Type
Current
Instruction Exception Event Priority * 1
Exception
Order
Process
at BL=1
Vector
Code
Vector
Offset
Power-on reset 1 1 Reset H'A00  Reset Aborted
Manual reset 1 2 Reset H'020 —
H-UDI reset 1 1 Reset H'000 —
User break
(before instruction execution)
2 0 Ignored H'1E0 H'00000100 General
exception
events
Re-executed
CPU address error
(instruction access) * 4
2 1 Reset H'0E0 H'00000100
Illegal general instruction exception 2 2 Reset H'180 H'00000100
Illegal slot instruction exception 2 2 Reset H'1A0 H'00000100
CPU address error (data access)* 4 2 3 Reset H'0E0/
H'100
H'00000100
Unconditional trap
(TRAPA instruction)
2 4 Reset H'160 H'00000100 Completed
User breakpoint
(After instruction execution, address)
2 5 Ignored H'1E0 H'00000100
User breakpoint
(Data break, I-BUS break)
2 5 Ignored H'1E0 H'00000100 General
exception
events
Completed
DMA address error 2 6 Retained H'5C0 H'00000100
General
interrupt
requests
Completed Interrupt requests 3 —* 2 Retained —* 3 H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest.
A reset has the highest priority. An interrupt is accepted only when general exceptions
are not requested.
2. For details on priorities in multiple interrupt sources, refer to section 10, Interrupt
Controller (INTC).
3. If an interrupt is accepted, the exception event register (EXPEVT) is not changed. The
interrupt source code is specified in interrupt source register 2 (INTEVT2). For details,
refer to section 10, Interrupt Controller (INTC).
4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code
and vector offset are specified.