Renesas SH7641 - Manual (Page 459)

Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 409 of 982
REJ09B0023-0400
13.3.1 DMA Source Address Registers (SAR)
DMA source address registers (SAR) are 32-bit read/write registers that specify the source address
of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When
the data of an external device with
DACK is transferred in the single address mode, the SAR is
ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value. The SAR is undefined at reset and retains the current value in standby or
module standby mode.
13.3.2 DMA Destination Address Registers (DAR)
DMA destination address registers (DAR) are 32-bit read/write registers that specify the
destination address of a DMA transfer. These registers include count functions, and during a DMA
transfer, these registers indicate the next destination address. When the data of an external device
with
DACK is transferred in the single address mode, the DAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the
source address value. The DAR is undefined at reset and retains the current value in standby or
module standby mode.
13.3.3 DMA Transfer Count Registers (DMATCR)
DMA transfer count registers (DMATCR) are 32-bit read/write registers that specify the DMA
transfer count (bytes, words, or longwords). The number of transfers is 1 when the setting is
H'000001, 16777215 when H'00FFFFFF is set, and 16777216 (the maximum) when H'000000 is
set. During a DMA transfer, these registers indicate the remaining transfer count.
The upper eight bits of DMATCR will return 0 if read, and should only be written with 0. To
transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The DMATCR is undefined at
reset and retains the current value in standby or module standby mode.