Renesas SH7641 - Manual (Page 556)

Section 16 I 2 C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 506 of 982
REJ09B0023-0400
16.5 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun error. Table 16.3 shows the
contents of each interrupt request.
Table 16.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
I
2 C Mode
Clocked
Synchronous
Mode
Transmit data Empty TXI (TDRE=1) • (TIE=1) { {
Transmit end TEI (TEND=1) • (TEIE=1) { {
Receive data full RXI (RDRF=1) • (RIE=1) { {
STOP recognition STPI (STOP=1) • (STIE=1) {
×
NACK receive {
×
Arbitration lost/
overrun error
NAKI {(NACKF=1)+(AL=1)} •
(NAKIE=1)
{ {
When the interrupt condition described in table 16.3 is 1, the CPU executes an interrupt exception
handling. Interrupt sources should be cleared in the exception handling. The TDRE and TEND
bits are automatically cleared to 0 by writing the transmit data to ICDRT. The RDRF bit is
automatically cleared to 0 by reading ICDRR. The TDRE bit is set to 1 again at the same time
when the transmit data is written to ICDRT. When the TDRE bit is cleared to 0, then an excessive
data of one byte may be transmitted.