Renesas SH7641 - Manual (Page 289)

Section 10 Interrupt Controller (INTC)
Rev. 4.00 Sep. 14, 2005 Page 239 of 982
REJ09B0023-0400
I3 to I0: Interrupt mask bits in status register (SR)
Program
execution state
Interrupt
generated?
SR.BL=0
or sleep mode?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
NMI?
Level 15
interrupt?
Set interrupt sourse in
INTEVT2
Save SR to SSR;
save PC to SPC
Set BL/RB
bits in SR to1
Branch to exception
handler
I3 to I0 level
14or lower?
Level 14
interrupt?
I3 to I0 level
13 or lower?
Level 1
interrupt?
I3 to I0
level 0?
Figure 10.2 Interrupt Operation Flowchart