Renesas SH7641 - Manual (Page 754)

Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 704 of 982
REJ09B0023-0400
Bit Bit Name
Initial
value R/W Description
2 PER 0 R Parity Error
Indicates a parity error in the data read from the next
receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No receive parity error occurred in the next data
read from SCFRDR
[Clearing conditions]
• PER is cleared to 0 when the chip undergoes a
power-on reset
• PER is cleared to 0 when no parity error is present
in the next data read from SCFRDR
1: A receive parity error occurred in the data read
from SCFRDR
[Setting condition]
• PER is set to 1 when a parity error is present in
the next data read from SCFRDR