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4 interrupt and dmac transfer request – Renesas SH7641 User Manual

Page 862

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Section 21 A/D Converter

Rev. 4.00 Sep. 14, 2005 Page 812 of 982

REJ09B0023-0400

21.4

Interrupt and DMAC Transfer Request

The A/D converter generates an interrupt (ADI0 and ADI1) or DMAC activation signal at the end
of A/D conversion. These requests are enabled or disabled by the ADIE bit or the DMASL bit in
ADCSR.

When the DMAC is activated by an ADI interrupt, the ADF bit in the A/D control/status register
(ADCSR0 and ADCSR1) is automatically cleared to 0 when an A/D register is accessed.

Table 21.5 Interrupt and DMAC Transfer Request

ADIE Bit

DMASL Bit

Interrupt

DMAC Transfer Request

0 Disabled

Disabled

0

1 Disabled

Enabled

0 Enabled

Disabled

1

1 Disabled

Enabled

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