Renesas SH7641 - Manual (Page 328)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 278 of 982
REJ09B0023-0400
• Refresh timer control/status register (RTCSR)
• Refresh timer counter (RTCNT)
• Refresh time constant register (RTCOR)
• Reset wait counter (RWTCNT)
12.4.1 Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area. This register is only
initialized by a power-on reset, and it is not initialized by a manual reset and in the standby mode.
Do not access external memory other than area 0 until the CMNCR register initialization is
complete.
Bit Bit Name
Initial
Value R/W Description
31 to 16  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
15 WAITSEL 0 R/W WAIT Signal Sampling Timing Specification
Specifies the external WAIT signal sampling timing.
0: Samples the WAIT signal at the falling edge of the
CKIO. In this case, the WAIT signal can be input
asynchronously.
1: Samples the WAIT signal at the rising edge of the
CKIO. In this case, the WAIT signal must be input
synchronously.
14, 13  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
12 MAP 0 R/W Space Specification
Selects the address map for the external address
space. The address maps to be selected are shown in
tables 12.2 and 12.3.
0: Selects address map 1.
1: Selects address map 2.