Renesas SH7641 - Manual (Page 25)

Rev. 4.00 Sep. 14, 2005 Page xxv of l
21.3.6 Input Sampling and A/D Conversion Time .......................................................... 810
21.4 Interrupt and DMAC Transfer Request.............................................................................. 812
21.5 Definitions of A/D Conversion Accuracy.......................................................................... 813
21.6 Usage Notes ....................................................................................................................... 815
21.6.1 Setting Analog Input Voltage ............................................................................... 815
21.6.2 Processing of Analog Input Pins........................................................................... 815
21.6.3 Permissible Signal Source Impedance .................................................................. 815
21.6.4 Influences on Absolute Precision.......................................................................... 816
21.6.5 Stop during A/D Conversion ................................................................................ 816
Section 22 Pin Function Controller (PFC).........................................................819
22.1 Register Descriptions ......................................................................................................... 823
22.1.1 Port A Control Register (PACR) .......................................................................... 824
22.1.2 Port B Control Register (PBCR)........................................................................... 826
22.1.3 Port C Control Register (PCCR)........................................................................... 827
22.1.4 Port D Control Register (PDCR) .......................................................................... 828
22.1.5 Port E Control Register (PECR) ........................................................................... 830
22.1.6 Port E I/O Register (PEIOR)................................................................................. 832
22.1.7 Port E MTU R/W Enable Register (PEMTURWER) ........................................... 833
22.1.8 Port F Control Register (PFCR)............................................................................ 834
22.1.9 Port G Control Register (PGCR) .......................................................................... 836
22.1.10 Port H Control Register (PHCR) .......................................................................... 838
22.1.11 Port J Control Register (PJCR) ............................................................................. 839
22.2 I/O Buffer Internal Block Diagram .................................................................................... 841
22.2.1 I/O Buffer with Weak Keeper............................................................................... 841
22.2.2 I/O Buffer with Open Drain Output...................................................................... 841
22.3 Notes on Usage .................................................................................................................. 842
Section 23 I/O Ports ...........................................................................................843
23.1 Port A................................................................................................................................. 843
23.1.1 Register Description ............................................................................................. 843
23.1.2 Port A Data Register (PADR)............................................................................... 844
23.2 Port B ................................................................................................................................. 845
23.2.1 Register Description ............................................................................................. 845
23.2.2 Port B Data Register (PBDR) ............................................................................... 846
23.3 Port C ................................................................................................................................. 847
23.3.1 Register Description ............................................................................................. 847
23.3.2 Port C Data Register (PCDR) ............................................................................... 848
23.4 Port D................................................................................................................................. 849
23.4.1 Register Description ............................................................................................. 850