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Renesas SH7641 User Manual

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Rev. 4.00 Sep. 14, 2005 Page 976 of 982

REJ09B0023-0400

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Section 25 Electrical
Characteristics

Figure 25.37 Synchronous
DRAM Auto-Refreshing
Timing

(WTRP = 1 Cycle, WTRC =
3 Cycles)

Figure 25.38 Synchronous
DRAM Self-Refreshing
Timing
(WTRP = 1 Cycle)

Figure 25.39 Synchronous
DRAM Mode Register
Write Timing (WTRP = 1
Cycle)

Figure 25.41 Synchronous
DRAM Self-Refreshing
Timing in Low-Frequency
Mode

(WTRP = 2 Cycles)

949 to
951
and

953

(Hi-Z)*

3

D31 to D0

Note: 1. An address pin to be connected to pin A10 of SDRAM.

2. Waveform for

DACKn when active low is selected.

3. Pins D31 to D16 with weak keeper are retained as weak keepers.

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