Renesas SH7641 - Manual (Page 306)

Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 256 of 982
REJ09B0023-0400
11.3 Operation
11.3.1 Flow of the User Break Operation
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses is set in the break address registers (BARA or BARB). The masked
addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is
set in the break data register (BDRB). The masked data is set in the break data mask register
(BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA or
BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select, instruction
fetch/data access select, and read/write select) are each set. No user break will be generated if
even one of these groups is set with 00. The respective conditions are set in the bits of the
break control register (BRCR). Make sure to set all registers related to breaks before setting
BBRA or BBRB.
2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and
sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match
flag (SCMFDA or SCMFDB) for the appropriate channel. When the X/Y memory bus is
specified for channel B, SCMFCB is used for the condition match flag.
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. 0 must first be written to them before they can be used again.
4. There is a chance that the break set in channel A and the break set in channel B occur around
the same time. In this case, there will be only one break request to the CPU, but these two
break channel match flags could be both set.
5. When selecting the I bus as the break condition, note the following:
 Several bus masters, including the CPU and DMAC, are connected to the I bus. The UBC
monitors bus cycles generated by all bus masters, and determines the condition match.
 Physical addresses are used for the I bus. Set a physical address in break address registers
(BARA and BARB). The upper three bits of logical addresses in the P0 to P3 area issued
by the CPU on the L bus are masked (to 0) before they are placed on the I bus. The upper
three bits of the source and destination addresses set in the DMAC are masked in the same
way. However, logical addresses in the P4 area are output unchanged on the I bus.
 For data access cycles issued on the L bus by the CPU, if their logical addresses are not to
be cached, they are issued with the data size specified on the L bus.
 For instruction fetch cycles issued on the L bus by the CPU, even though their logical
addresses are not to be cached, they are issued in longwords and their addresses are
rounded to match longword boundaries.