Renesas SH7641 - Manual (Page 642)

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 592 of 982
REJ09B0023-0400
Table 18.40 Register Settings for Complementary PWM Mode
Channel Counter/Register Description Read/Write from CPU
3 TCNT_3 Start of up-count from value set
in dead time register Maskable by
PTE/PEMTURWE setting*
TGRA_3 Set TCNT_3 upper limit value
(1/2 carrier cycle + dead time) Maskable by
PTE/PEMTURWE setting*
TGRB_3 PWM output 1 compare register Maskable by
PTE/PEMTURWE setting*
TGRC_3 TGRA_3 buffer register Always readable/writable
TGRD_3 PWM output 1/TGRB_3 buffer
register Always readable/writable
4 TCNT_4 Up-count start, initialized to
H'0000 Maskable by
PTE/PEMTURWE setting*
TGRA_4 PWM output 2 compare register Maskable by
PTE/PEMTURWE setting*
TGRB_4 PWM output 3 compare register Maskable by
PTE/PEMTURWE setting*
TGRC_4 PWM output 2/TGRA_4 buffer
register Always readable/writable
TGRD_4 PWM output 3/TGRB_4 buffer
register Always readable/writable
Timer dead time data register
(TDDR) Set TCNT_4 and TCNT_3 offset
value (dead time value) Maskable by
PTE/PEMTURWE setting*
Timer cycle data register
(TCDR) Set TCNT_4 upper limit value
(1/2 carrier cycle) Maskable by
PTE/PEMTURWE setting*
Timer cycle buffer register
(TCBR) TCDR buffer register Always readable/writable
Subcounter (TCNTS) Subcounter for dead time
generation Read-only
Temporary register 1 (TEMP1) PWM output 1/TGRB_3
temporary register Not readable/writable
Temporary register 2 (TEMP2) PWM output 2/TGRA_4
temporary register Not readable/writable
Temporary register 3 (TEMP3) PWM output 3/TGRB_4
temporary register Not readable/writable
Note: * Access can be enabled or disabled according to the setting of bit 0 (MTURWE) in
PTE/PEMTURWE (port E/port E MTU R/W enable register).