Renesas SH7641 - Manual (Page 291)

Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 241 of 982
REJ09B0023-0400
Section 11 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
11.1 Features
The UBC has the following features:
1. The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
• Address
Comparison bits are maskable in 1-bit units.
One of the four address buses (logic address bus (LAB), internal address bus (IAB),
X-memory address bus (XAB), and Y-memory address bus (YAB)) can be selected.
• Data
Only on channel B, 32-bit maskable.
One of the four data buses (L-bus data (LDB), I-bus data (IDB), X-memory data bus (XDB)
and Y-memory data bus (YDB)) can be selected.
• Bus cycle
Instruction fetch or data access
• Read/write
• Operand size
Byte, word, and longword
2. A user-designed user-break condition exception processing routine can be run.
3. In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
4. Maximum repeat times for the break condition (only for channel B): 2 12 − 1 times.
5. Eight pairs of branch source/destination buffers.