Renesas SH7641 - Manual (Page 338)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 288 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
1
0
HW1
HW0
0
0
R/W
R/W
Delay Cycles from RD,
WEn Negation to Address, CSn
Negation
Specify the number of delay cycles from RD and
WEn
negation to address and
CSn negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Note: * To connect the burst ROM to the CS0 area and use the burst ROM interface after the
BSC is activated, enables the burst access through bit 20, specifies the number of burst
wait cycles through bits 17 and 16, and then set the bits TYPE[2:0] in CS0BCR.
Reserved bits other than above should not be set to 1.
For details on the burst ROM interface, see Burst ROM (Clock Asynchronous).
• CS2WCR, CS3WCR
Bit Bit Name
Initial
Value R/W Description
31 to 21  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 BAS 0 R/W Byte-Selection SRAM Byte Access Selection
Specifies the
WEn and RD/WR signal timing when the
byte-selection SRAM interface is used.
0: Asserts the
WEn signal at the read timing and
asserts the RD/
WR signal during the write access
cycle.
1: Asserts the
WEn signal during the read access cycle
and asserts the RD/
WR signal at the write timing.
19 to 11
 All
0 R Reserved
These bits are always read as 0. The write value
should always be 0.