Renesas SH7641 - Manual (Page 493)

Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 443 of 982
REJ09B0023-0400
To execute a longword access to an 8-bit or 16-bit external device or to execute a word access to
an 8-bit external device, the
DACK and TEND outputs are divided for data alignment as shown in
figure 13.18.
CKIO
Address
DACKn
TENDn
WAIT
CSn
T
1
T
2
T
aw
T
1
T
2
(Active low)
(Active low)
Note: TEND is asserted for the last transfer unit of DMA transfers.
If a transfer unit is divided into multiple bus cycles and
if
CSn is negated during the bus cycle, TEND is also divided.
RD
D15 to D0
WEn
D15 to D0
Read
Write
Figure 13.18 BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)