Renesas SH7641 - Manual (Page 496)

Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 446 of 982
REJ09B0023-0400
6. Note the followings when the DMA transfer request is sent from the SCIF.
Even when the DMAC has completed the TCR times of transfers (the TE bit in CHCR = 1),
the DMAC accepts and keeps the transfer request from the SCIF (max. one time of transfer) if
all the conditions shown below are satisfied. The DMA transfer, however, is not executed
because the TE bit is set to 1. Clearing the TE bit in this condition can immediately restart the
transfer.
Conditions that make the DMA transfer request acceptable:
 The DME bit in the DMA operation register (DMAOR) is set to 1.
 The DE bit in the DMA channel control register (CHCR) is set to 1.
 The peripheral module SCIF is set to the DMA extension resource selector (DMARS).
Take special care when the SCIF transfer is executed by the DMAC. If the transfer restart is
not desired, prevent the transfer from restarting by implementing one of the measures shown
below.
Preventive measures:
 Clear the DE bit of CHCR in the end interrupt routine of the DMAC. (The DMA transfer
request from the SCIF is not accepted.) In this case, set the end interrupt of the DMAC to
have the highest priority.
 Set 1 to TCR, and dummy addresses to SAR and DAR, respectively. Then perform the
dummy transfer to clear the transfer request in the DMAC.
13.4.8 Notes On DREQ Sampling When DACK is Divided in External Access
(1) Error Phenomenon
When the DACK output is divided in an external access, DREQ may be sampled twice at
maximum in the external access.
(2) Error Conditions and Phenomenon
Conditions: The DACK output is divided in an external access when:
• 16-byte access,
• 32-bit access to the 8-bit space,
• 16-bit access to the 8-bit space, or
• 32-bit access to the 16-bit space
is performed with either of the following idle cycle settings made:
• Idle cycles between write-write cycles (IWW = 01 or more)