Renesas SH7641 User Manual
Page 391
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 341 of 982
REJ09B0023-0400
Table 12.8 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(1)-2
Setting
BSZ
1, 0
A2/3
ROW
1, 0
A2/3
COL
1, 0
11 (32 bits)
00 (11 bits)
00 (8 bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
SDRAM Pin
Function
A17 A25 A17
A16 A24 A16
A15 A23*
2
A23*
2
Unused
A14 A22*
2
A22*
2
A13
(BA1)
A13 A21 A13
A12
(BA0)
Specifies bank
A12 A20*
2
L/H*
1
A10/AP Specifies
address/precharge
A11 A19 A11
A9
A10 A18 A10
A8
A9 A17 A9
A7
A8 A16 A8
A6
A7 A15 A7
A5
A6 A14 A6
A4
A5 A13 A5
A3
A4 A12 A4
A2
A3 A11 A3
A1
A2 A10 A2
A0
Address
A1 A9 A1
A0 A8 A0
Unused
Example of connected memory
128-Mbit product (1 Mword
× 32 bits × 4 banks, column 8 bits product): 1
64-Mbit product (1 Mword
× 16 bits × 4 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2.
Bank
address
specification