Renesas SH7641 - Manual (Page 550)

Section 16 I 2 C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 500 of 982
REJ09B0023-0400
1 2 7 8 1 7 8 1 2 SCL
MST
TRS
RDRF
ICDRS
ICDRR
SDA
(Input)
Bit 0 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 Bit 1 Bit 1
User
processing
Data 1
Data 1
Data 2
Data 2
Data 3
[2] Set MST
(when outputting the clock)
[3] Read ICDRR [3] Read ICDRR
Figure 16.15 Receive Mode Operation Timing
SDA
(Input)
Bit 0
1 2 3 4 5 6 7 8
000
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
SCL
MST
RCVD
BC2 to BC0
[2] Set MST
111 110 101 100 011 010 001 000
[3] Set the RCVD bit after checking if BSC2 = 1
Figure 16.16 Operation Timing For Receiving One Byte