Renesas SH7641 - Manual (Page 152)

Section 3 DSP Operation
Rev. 4.00 Sep. 14, 2005 Page 102 of 982
REJ09B0023-0400
Negative Value Mode: CS[2:0] = 001: The DC flag indicates the same state as the MSB of the
operation result. When the result is a negative number, the DC bit shows 1. When it is a positive
number, the DC bit shows 0. The ALU always executes 40-bit arithmetic operation, so the sign bit
to detect whether positive or negative is always got from the MSB of the operation result
regardless of the destination operand. Some examples are shown in figure 3.4.
Example 1
Sign bit
Guard bits
Negative value
1100
0000
+)
0000
0000 0000
0000 0000
0000 0000
0000 0000
0001
1100 0000 0000 0000 0000 0001
Example 2
Sign bit
Guard bits
Positive value
0011
0000
+)
0000
0000 0000
1000 0000
0000 0000
0000 0000
0001
0011 0000 1000 0000 0000 0001
Figure 3.4 DC Bit Generation Examples in Negative Value Mode
Zero Value Mode: CS[2:0] = 010: The DC flag indicates whether the operation result is 0 or not.
When the result is 0, the DC bit shows 1. When it is not 0, the DC bit shows 0.
Overflow Mode: CS[2:0] = 011: The DC bit indicates whether or not overflow occurs in the
result. When an operation yields a result beyond the range of the destination register, except the
guard-bit parts, the DC bit is set. Even though guard bits are provided, the DC bit always indicates
the result of when no guard bits are provided. So, the DC bit is always set if the guard-bit parts are
used for large number representation. Some DC bit generation examples in overflow mode are
shown in figure 3.5.
Example 1
Overflow detecting field
Guard bits
Overflow case
1111
1111
+)
1111
1111 1111
1000 1111
0000 1111
0000 1111
0000
1111 1111 0111 1111 1111 1111
Example 2
Overflow detecting field
Guard bits
Non overflow case
1111
1111
+)
1111
1111 1111
1000 1111
0000 1111
0000 1111
0001
1111 1111 1000 0000 0000 0000
Figure 3.5 DC Bit Generation Examples in Overflow Mode