Renesas SH7641 - Manual (Page 361)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 311 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
15 to 11  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10
9
8
7
W3
W2
W1
W0
1
0
1
0
R/W
R/W
R/W
R/W
Number of Access Wait Cycles
Specify the number of wait cycles to be inserted in the
first access cycle.
0000: No cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (Setting prohibited)
1110: Reserved (Setting prohibited)
1111: Reserved (Setting prohibited)
6 WM 0 R/W External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
5 to 0  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.