A.2 when i/o port is selected – Renesas SH7641 User Manual
Page 1021

Appendix
Rev. 4.00 Sep. 14, 2005 Page 971 of 982
REJ09B0023-0400
A.2
When I/O Port is Selected
Table A.2
Pin States in Reset State, Power Down Mode, and Bus-Released States When
I/O Port is Selected
Reset State
Power Down Mode
Pin Name
Power-On
Manual
Software
Standby Sleep
Bus-Released
Reset
PTA[14:0] Z+
I+/O
Z+/K* I+/O I+/O
PTB[8:0] Z+
I+/O
Z+/K* I+/O I+/O
PTC[15,14,12:0] Z+
I+/O
Z+/K* I+/O I+/O
PTC[13] O
I+/O
Z+/K* I+/O I+/O
PTD[15:0] Z+
I+/O
Z+/K* I+/O I+/O
PTE[15:0] Z+
I+/O
Z+/K* I+/O I+/O
PTF[15:0] Z+
I+/O
Z+/K* I+/O I+/O
PTG[13:11,8] Z+ I+/O Z+/K* I+/O I+/O
PTG[10:9] Z I/O
Z+/K* I/O I/O
PTG[7:0] Z I Z I
I
PTH[14:0] Z+
I+/O
Z+/K* I+/O I+/O
PTJ[12:0] Z+
I+/O
Z+/K* I+/O I+/O
[Legend]
I: Input
I+:
Input with weak keeper
O: Output
Z:
Hi-Z (The pin must not be open since the intermediate level at this pin causes a path though
current in the LSI.)
Z+: Hi-Z with weak keeper
K:
Input becomes Hi-Z, output retains state
Note: * Controlled by the HIZ bit in the standby control register.