Renesas SH7641 - Manual (Page 279)

Section 10 Interrupt Controller (INTC)
Rev. 4.00 Sep. 14, 2005 Page 229 of 982
REJ09B0023-0400
10.3.6 Interrupt Mask Registers 0 to 10 (IMR0 to IMR10)
IMR0 to IMR10 are 8-bit readable/writable registers that mask the
IRQ and on-chip peripheral
module interrupts. When an interrupt source is masked, interrupt requests may be mistakenly
detected, depending on the operation state of the IRQ pins and on-chip peripheral modules. To
prevent this, set IMR0 to IMR9 while no interrupts are set to be generated, and then read the new
settings from these registers.
Table 10.3 shows the relationship between IMR and each interrupt source.
Bit Bit Name
Initial
Value R/W
Description
7
6
5
4
3
2
1
0
IM7
IM6
IM5
IM4
IM3
IM2
IM1
IM0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt Mask
Table 10.3 lists the correspondence between the
interrupt sources and interrupt mask registers.
IMn
1: Interrupt source of the corresponding bit is masked.
0: When reading, Interrupt source of the corresponding
bit is not masked. When writing, No processing.
n = 7 to 0