Renesas SH7641 - Manual (Page 461)

Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 411 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Descriptions
21 to 18  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
17 AM 0 R/W Acknowledge Mode
AM specifies whether
DACK is output in data read
cycle or in data write cycle in dual address mode.
In single address mode,
DACK is always output
regardless of the specification by this bit.
This bit is valid only in CHCR_0 and CHCR_1.This bit
is always read as 0 in CHCR_2 and CHCR_3. The
write value should always be 0.
0:
DACK output in read cycle (Dual address mode)
1:
DACK output in write cycle (Dual address mode)
16 AL 0 R/W Acknowledge Level
AL specifies the
DACK (acknowledge) signal output is
high active or low active.
This bit is valid only in CHCR_0 and CHCR_1.This bit
is always read as 0 in CHCR_2 and CHCR_3. The
write value should always be 0.
0: Low-active output of
DACK
1: High-active output of
DACK
15
14
DM1
DM0
0
0
R/W
R/W
Destination Address Mode
DM1 and DM0 select whether the DMA destination
address is incremented, decremented, or left fixed. (In
single address mode, DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address (Setting prohibited in 16-
byte transfer)
01: Destination address is incremented (+1 in 8-bit
transfer, +2 in 16-bit transfer, +4 in 32-bit transfer,
+16 in 16-byte transfer)
10: Destination address is decremented (–1 in 8-bit
transfer, –2 in 16-bit transfer, –4 in 32-bit transfer;
illegal setting in 16-byte transfer)
11: Reserved (Setting prohibited)