Renesas SH7641 - Manual (Page 101)

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 51 of 982
REJ09B0023-0400
Addressing
Mode Instruction
Format
Effective Address Calculation Method
Calculation Formula
Immediate #imm:8 8-bit immediate data imm of TST, AND, OR,
or XOR instruction is zero-extended. 
#imm:8 8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended. 
#imm:8 8-bit immediate data imm of TRAPA
instruction
is zero-extended and multiplied by 4. 
2.4.2 DSP Data Addressing
Two different memory accesses are made with DSP instructions. The two kinds of instructions are
X and Y data transfer instructions (MOVX.W and MOVY.W) and single data transfer instructions
(MOVS.W and MOVSL). The data addressing is different for these two kinds of instructions. An
overview of the data transfer instructions is given in table 2.12.
Table 2.12 Overview of Data Transfer Instructions
X/Y Data Transfer Processing
(MOVX.W, MOVY.W) Single Data Transfer Processing
(MOVS.W, MOVS.L)
Address register Ax: R4, R5, Ay: R6, R7 As: R2, R3, R4, R5
Index register Ix: R8, Iy: R9 Is: R8
Nop/Inc (+2)/index addition:
post-increment Nop/Inc (+2, +4)/index addition:
post-increment Addressing
 Dec (–2, –4): pre-decrement
Modulo addressing Possible Not possible
Data bus XDB, YDB LDB
Data length 16 bits (word) 16/32 bits (word/longword)
Bus contention No Yes
Memory X/Y data memory Entire memory space
Source register Dx, Dy: A0, A1 Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G
Destination register Dx: X0/X1, Dy: Y0/Y1 Ds: A0/A1, M0/M1, X0/X1, Y0/Y1, A0G, A1G