Renesas SH7641 - Manual (Page 118)

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 68 of 982
REJ09B0023-0400
Type Kinds of
Instruction
Op Code
Function Number of
Instructions
21 MUL Double-precision multiplication
(32
× 32 bits)
34
MULS Signed multiplication (16 × 16 bits)
Arithmetic
operation
instructions
MULU Unsigned multiplication (16 × 16 bits)
NEG Sign inversion
NEGC Sign inversion with borrow
SUB Binary subtraction
SUBC Binary subtraction with carry
SUBV Binary subtraction with underflow
Logic 6 AND Logical AND 14
operation NOT Bit inversion
instructions OR Logical OR
TAS Memory test and bit setting
TST Logical AND and T bit setting
XOR Exclusive logical OR
Shift 12 ROTL 1-bit left rotation 16
instructions ROTR 1-bit right rotation
ROTCL 1-bit left rotation with T bit
ROTCR 1-bit right rotation with T bit
SHAL Arithmetic 1-bit left shift
SHAR Arithmetic 1-bit right shift
SHLL Logical 1-bit left shift
SHLLn Logical n-bit left shift
SHLR Logical 1-bit right shift
SHLRn Logical n-bit right shift
SHAD Arithmetic dynamic shift
SHLD Logical dynamic shift