Renesas SH7641 - Manual (Page 393)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 343 of 982
REJ09B0023-0400
Table 12.9 Relationship between BSZ1, 0, A2/3ROW1, 0, and Address Multiplex Output
(2)-2
Setting
BSZ
1, 0 A2/3
ROW
1, 0 A2/3
COL
1, 0
11 (32 bits) 00 (11 bits) 00 (8 bits)
Output Pin of
This LSI Row Address
Output Cycle Column Address
Output Cycle SDRAM Pin Function
A17 A27 A17
A16 A26 A16
Unused
A15 A25* 2 A25* 2 * 3 A13 (BA1)
A14 A24* 2 A24* 2 A12 (BA0)
Specifies bank
A13 A23 A13 A11 Address
A12 A22 L/H* 1 A10/AP Specifies
address/precharge
A11 A21 A11 A9
A10 A20* 2 A10 A8
A9 A19 A9 A7
A8 A18 A8 A6
A7 A17 A7 A5
A6 A16 A6 A4
A5 A15 A5 A3
A4 A14 A4 A2
A3 A13 A3 A1
A2 A12 A2 A0
Address
A1 A11 A1
A0 A10 A0
Unused
Example of connected memory
512-Mbit product (4 Mwords × 32 bits × 4 banks, column 10 bits product): 1
256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification
3. Only the
RASL pin is asserted because the A25 pin specified the bank address. RASU
is not asserted.