Renesas SH7641 - Manual (Page 281)

Section 10 Interrupt Controller (INTC)
Rev. 4.00 Sep. 14, 2005 Page 231 of 982
REJ09B0023-0400
10.3.7 Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10)
IMCR0 to IMCR10 are 8-bit writable registers that clear the mask settings for the
IRQ and on-
chip peripheral module interrupts. Table 10.4 shows the relationship between IMCR and each
interrupt source.
Bit Bit Name
Initial
Value R/W
Description
7
6
5
4
3
2
1
0
IMC7
IMC6
IMC5
IMC4
IMC3
IMC2
IMC1
IMC0







 W
W
W
W
W
W
W
W
Interrupt Mask Clear
Table 10.4 lists the correspondence between the
interrupt sources and interrupt mask clear registers.
IMCn (Write)
1: The corresponding bit in interrupt mask register
IMCn is cleared
0: No processing
n = 7 to 0