Renesas SH7641 - Manual (Page 208)

Section 5 Watchdog Timer (WDT)
Rev. 4.00 Sep. 14, 2005 Page 158 of 982
REJ09B0023-0400
Bit Bit Name
Initial
Value R/W Description
4 WOVF 0 R/W Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
3 IOVF 0 R/W Interval Timer Overflow
Indicates that the WTCNT has overflowed in interval
timer mode. This bit is not set in watchdog timer
mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (P
φ). The overflow period that is
shown inside the parenthesis in the table is the value
when the peripheral clock (P
φ) is 15 MHz.
Bits 2 to 0 Clock Ratio Overflow Cycle
000: 1 17 us
001: 1/4 68 us
010: 1/16 273 us
011: 1/32 546 us
100: 1/64 1.09 ms
101: 1/256 4.36 ms
110: 1/1024 17.48 ms
111: 1/4096 69.91 ms
Note: If bits CKS2 to CKS0 are modified when the
WDT is running, the up-count may not be
performed correctly. Ensure that these bits are
modified only when the WDT is not running.
In addition, the timing of the first overflow
includes deviation. See section 5.4,
Precautions to Take when Using the WDT.