Renesas SH7641 User Manual
Page 20
Rev. 4.00 Sep. 14, 2005 Page xx of l
16.3.9
I
2
C Bus Shift Register (ICDRS)............................................................................ 487
16.3.10
NF2CYC Register (NF2CYC).............................................................................. 487
16.4
Operation ........................................................................................................................... 488
16.4.1
I
2
C Bus Format...................................................................................................... 488
16.4.2
Master Transmit Operation ................................................................................... 489
16.4.3
Master Receive Operation .................................................................................... 491
16.4.4
Slave Transmit Operation ..................................................................................... 493
16.4.5
Slave Receive Operation....................................................................................... 496
16.4.6
Clocked Synchronous Serial Format .................................................................... 497
16.4.7
Noise Filter ........................................................................................................... 501
16.4.8
Example of Use..................................................................................................... 502
16.5
Interrupt Request................................................................................................................ 506
16.6
Bit Synchronous Circuit..................................................................................................... 507
16.7
Usage Note......................................................................................................................... 508
Section 17 Compare Match Timer (CMT) ........................................................ 509
17.1
Features.............................................................................................................................. 509
17.2
Register Descriptions ......................................................................................................... 510
17.2.1
Compare Match Timer Start Register (CMSTR) .................................................. 510
17.2.2
Compare Match Timer Control/Status Register (CMCSR) .................................. 511
17.2.3
Compare Match Counter (CMCNT ) .................................................................... 512
17.2.4
Compare Match Constant Register (CMCOR) ..................................................... 512
17.3
Operation ........................................................................................................................... 513
17.3.1
Interval Count Operation ...................................................................................... 513
17.3.2
CMCNT Count Timing......................................................................................... 513
17.4
Compare Matches .............................................................................................................. 514
17.4.1
Timing of Compare Match Flag Setting ............................................................... 514
17.4.2
DMA Transfer Requests and Interrupt Requests .................................................. 514
17.4.3
Timing of Compare Match Flag Clearing............................................................. 515
Section 18 Multi-Function Timer Pulse Unit (MTU)........................................ 517
18.1
Features.............................................................................................................................. 517
18.2
Input/Output Pins ............................................................................................................... 521
18.3
Register Descriptions ......................................................................................................... 522
18.3.1
Timer Control Register (TCR).............................................................................. 524
18.3.2
Timer Mode Register (TMDR)............................................................................. 528
18.3.3
Timer I/O Control Register (TIOR) ...................................................................... 530
18.3.4
Timer Interrupt Enable Register (TIER)............................................................... 548
18.3.5
Timer Status Register (TSR)................................................................................. 550
18.3.6
Timer Counter (TCNT)......................................................................................... 553