Renesas SH7641 - Manual (Page 748)

Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 698 of 982
REJ09B0023-0400
Bit Bit Name
Initial
value R/W
Description
2  0 R Reserved
This bit is always read as 0. The write value should
always be 0.
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 1, 0
Select the SCIF clock source and enable or disable
clock output from the SCK pin. Depending on the
combination of CKE1 and CKE0, the SCK pin can be
used for serial clock output or serial clock input.
If the serial clock output is set in synchronous mode,
the communication mode bit (C/
A) in SCSMR2 is set to
1, and then CKE1 and CKE0 bits are set.
• Asynchronous mode
00: Internal clock, SCK pin used for input pin (input
signal is ignored)
01: Internal clock, SCK pin used for clock output
(The output clock frequency is 16 times the bit rate.)
10: External clock, SCK pin used for clock input
(The input clock frequency is 16 times the bit rate.)
11: Setting prohibited
• Synchronous mode
00: Internal clock, SCK pin used for serial clock output
01: Internal clock, SCK pin used for serial clock output
10: External clock, SCK pin used for serial clock input
11: Setting prohibited