Renesas SH7641 - Manual (Page 117)

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 67 of 982
REJ09B0023-0400
2.5 Instruction Set
2.5.1 CPU Instruction Set
The SH-1/SH-2/SH-3 compatible instruction set consists of 67 basic instruction types divided into
seven functional groups, as shown in table 2.18. Tables 2.19 to 2.24 show the instruction notation,
machine code, execution time, and function.
Table 2.18 CPU Instruction Types
Type Kinds of
Instruction
Op Code
Function Number of
Instructions
Data transfer
instructions
5 MOV Data transfer
Immediate data transfer
Peripheral module data transfer
Structure data transfer
39
MOVA Effective address transfer
MOVT T bit transfer
SWAP Upper/lower swap
XTRCT Extraction of middle of linked registers
Arithmetic 21 ADD Binary addition 34
operation ADDC Binary addition with carry
instructions ADDV Binary addition with overflow check
CMP/cond Comparison
DIV1 Division
DIV0S Signed division initialization
DIV0U Unsigned division initialization
DMULS Signed double-precision multiplication
DMULU Unsigned double-precision
multiplication
DT Decrement and test
EXTS Sign extension
EXTU Zero extension
MAC Multiply-and-accumulate, double-
precision multiply-and-accumulate