Renesas SH7641 User Manual
Page 435
Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 385 of 982
REJ09B0023-0400
Tm1
Tmd1w
Tmd1
Tmd2
Tmd3
Tmd4
A
D0
D1
D2
D3
Note: * The waveform for
DACKn is when active low is specified.
CKIO
D31 to D0
A25 to A0
FRAME
CS6B
RD/
WR
WAIT
BS
DACKn*
Figure 12.45 Burst MPX Space Access Timing
(Burst Read, No Wait, or Software Wait 1, CS6BWCR.MPXMD = 0)
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