Renesas SH7641 - Manual (Page 486)

Section 13 Direct Memory Access Controller (DMAC)
Rev. 4.00 Sep. 14, 2005 Page 436 of 982
REJ09B0023-0400
Figure 13.8 shows example of DMA transfer timing in single address mode.
Address output to external memory space
Select signal to external memory space
Select signal to external memory space
Data output from external device with DACK
DACK signal (active-low) to external device with DACK
Write strobe signal to external memory space
Address output to external memory space
Data output from external memory space
DACK signal (active-low) to external device with DACK
Read strobe signal to external memory space
(a) External device with DACK → external memory space (ordinary memory)
(b) External memory space (ordinary memory) → external device with DACK
CK
A25 to A0
D31 to D0
DACKn
CSn
WE
CK
A25 to A0
D31 to D0
DACKn
CSn
RD
Figure 13.8 Example of DMA Transfer Timing in Single Address Mode
Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TB bits of the
channel control register (CHCR).
1. Cycle-Steal Mode
• Normal mode
In the normal mode of cycle-steal, the bus mastership is given to another bus master after a
one-transfer-unit (byte, word, longword, or 16 bytes unit) DMA transfer. When another
transfer request occurs, the bus masterships are obtained from the other bus master and a
transfer is performed for one transfer unit. When that transfer ends, the bus mastership is
passed to the other bus master. This is repeated until the transfer end conditions are satisfied.
In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer
request source, transfer source, and transfer destination.