Renesas SH7641 - Manual (Page 534)

Section 16 I 2 C Bus Interface 2 (IIC2)
Rev. 4.00 Sep. 14, 2005 Page 484 of 982
REJ09B0023-0400
16.3.5 I 2 C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that confirms interrupt request flags and their status.
ICSR is initialized to H'00 by a power-on reset.
Bit Bit Name
Initial
Value R/W
Description
7 TDRE 0 R/W Transmit Data Register Empty
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When the start condition (including retransmission)
is issued
• When slave mode is changed from receive mode to
transmit mode
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT
6 TEND 0 R/W Transmit End
[Setting conditions]
• When the ninth clock of SCL rises with the I 2 C bus
format while the TDRE flag is 1
• When the final bit of transmit frame is sent with the
clock synchronous serial format
[Clearing conditions]
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT with an instruction
5 RDRF 0 R/W Receive Data Register Full
[Setting condition]
• When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When ICDRR is read with an instruction