Renesas SH7641 - Manual (Page 682)

Section 18 Multi-Function Timer Pulse Unit (MTU)
Rev. 4.00 Sep. 14, 2005 Page 632 of 982
REJ09B0023-0400
18.7.8 Conflict between TGR Read and Input Capture
If an input capture signal is generated in the T2 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 18.76 shows the timing in this case.
Input capture
signal
Read signal
Address
P φ
TGR
TCNT
Buffer register read cycle
T1 T2
M
N
N
Buffer register
M
Buffer register
address
Figure 18.76 Conflict between TGR Read and Input Capture