Renesas SH7641 - Manual (Page 431)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 381 of 982
REJ09B0023-0400
A15
A0
CS
OE
WE
I/O15
I/O0
UB
LB
. . .
. . .
. . .
A17
A2
CSn
RD
RD/ WR
D31
D16
WE3
WE2
D15
D0
WE1
WE0
This LSI
. . .
A15
A0
CS
OE
WE
I/O15
I/O0
UB
LB
. . .
. . .
. . .
64k × 16-bit
SRAM
Figure 12.40 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM
This LSI
A16
A1
CSn
RD
RD/ WR
D15
D0
WE1
WE0
A15
A0
CS
OE
WE
I/O 15
I/O 0
UB
LB
64k × 16-bit
SRAM
Figure 12.41 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM