Renesas SH7641 - Manual (Page 362)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 312 of 982
REJ09B0023-0400
Burst ROM (Clock Synchronous):
• CS0WCR
Bit Bit Name
Initial
Value R/W Description
31 to 18  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
17
16
BW1
BW0
0
0
R/W
R/W
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or later access cycles in burst
access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11  All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.