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Renesas SH7641 User Manual

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Section 25 Electrical Characteristics

Rev. 4.00 Sep. 14, 2005 Page 951 of 982

REJ09B0023-0400

Trc

Trc

Trc

Tmw

Tde

Trr

Trr

Tpw

Tp

Trc

t

CSD1

t

AD1

t

AD1

t

AD1

PALL

REF

REF

MRS

t

RWD1

t

RWD1

t

RWD1

t

CSD1

t

CSD1

t

CSD1

t

RASD1

t

RASD1

t

RASD1

t

RASD1

t

AD1

t

AD1

t

CASD1

t

CASD1

(Hi-Z)*

3

t

CSD1

t

CSD1

t

RASD1

t

RASD1

t

CASD1

t

CASD1

t

CSD1

t

CSD1

t

RWD1

t

RWD1

t

RASD1

t

RASD1

t

CASD1

t

CASD1

CKIO

A25 to A0

CSn

RD/

WR

A12/A11*

1

D31 to D0

RASU/L

CASU/L

BS

CKE

DQMxx

DACKn*

2

Note:

1. An address pin to be connected to pin A10 of SDRAM.

2. Waveform for

DACKn when active low is selected.

3. Pins D31 to D16 with weak keeper are retained as weak keepers.

Figure 25.39 Synchronous DRAM Mode Register Write Timing (WTRP = 1 Cycle)

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