Renesas SH7641 - Manual (Page 453)

Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 403 of 982
REJ09B0023-0400
DMA source and destination addresses exist in external memory space, the next write cycle will
not be initiated until the previous write cycle is completed.
If BSC registers are modified while the write buffer is functioning, correct access cannot be
performed. Thus, do not modify BSC registers immediately after the writing has finished. If BSC
registers need to be modified, modify the registers after dummy reading the write data.
On-Chip Peripheral Module Access: To access an on-chip module register, two or more
peripheral module clock (P
φ) cycles are required. Care must be taken in system design.