Renesas SH7641 - Manual (Page 75)

Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 25 of 982
REJ09B0023-0400
Section 2 CPU
2.1 Registers
This LSI has the same registers as the SH-3. In addition, this LSI also supports the same DSP-
related registers as in the SH-DSP. The basic software-accessible registers are divided into four
distinct groups:
• General registers
• Control registers
• System registers
• DSP registers
With the exception of some DSP registers, all of these registers are 32-bit width. The general
registers are accessible, with R0 to R7 banked to provide access to a separate set of R0 to R7
registers (i.e. R0 to R7_BANK0, and R0 to R7_BANK1)
depending on the value of the RB bit . The
register bank (RB) bit in the status register (SR) defines which set of banked registers (R0 to
R7_BANK0 or R0 to R7_BANK1) are accessed as general registers, and which are accessed only
by LDC/STC instructions.
The control registers can be accessed by LDC/STC instructions. Control registers are:
• SR: Status register
• SSR: Saved status register
• SPC: Saved program counter
• GBR: Global base register
• VBR: Vector base register
• RS: Repeat start register (DSP mode only)
• RE: Repeat end register (DSP mode only)
• MOD: Modulo register (DSP mode only)